UD=0, OADTYF=0, OADTYR=0, OADTY=00, UDF=0, OBDTY=00, OBDTYR=0, OBDTYF=0
General PWM Timer Count Direction and Duty Setting Register
UD | Count Direction Setting 0 (0): GTCNT counts down 1 (1): GTCNT counts up |
UDF | Forcible Count Direction Setting 0 (0): Not forcibly set 1 (1): Forcibly set |
OADTY | GTIOCnA Output Duty Setting 0 (00): GTIOCnA pin duty depends on the compare match 1 (01): GTIOCnA pin duty depends on the compare match 2 (10): GTIOCnA pin duty 0% 3 (11): GTIOCnA pin duty 100% |
OADTYF | Forcible GTIOCnA Output Duty Setting 0 (0): Not forcibly set 1 (1): Forcibly set |
OADTYR | GTIOCnA Output Value Selecting after Releasing 0%/100% Duty Setting 0 (0): The function selected by the GTIOA[3:2] bits is applied to the output value when the duty cycle is set after release from the 0 or 100% duty-cycle setting. 1 (1): The function selected by the GTIOA[3:2] bits is applied to the compare match output value which is masked after release from the 0 or 100% duty-cycle setting. |
OBDTY | GTIOCnB Output Duty Setting 0 (00): GTIOCnB pin duty depends on the compare match 1 (01): GTIOCnB pin duty depends on the compare match 2 (10): GTIOCnB pin duty 0% 3 (11): GTIOCnB pin duty 100% |
OBDTYF | Forcible GTIOCnB Output Duty Setting 0 (0): Not forcibly set 1 (1): Forcibly set |
OBDTYR | GTIOCnB Output Value Selecting after Releasing 0%/100% Duty Setting 0 (0): The function selected by the GTIOB[3:2] bits is applied to the output value when the duty cycle is set after release from the 0 or 100% duty-cycle setting. 1 (1): The function selected by the GTIOB[3:2] bits is applied to the compare match output value which is masked after release from the 0 or 100% duty-cycle setting. |